1. Field of the Invention
The present invention relates generally to pipeline analog-to-digital converter, and more particularly, to a stage of a pipeline ADC, wherein the stage comprises two split paths and uses level-shifting technique to generate a residue.
2. Description of the Prior Art
An analog-to-digital converter (ADC) is an electronic device that converts an input analog voltage or current to a digital number proportional to the magnitude of the voltage or current. ADCs are used virtually everywhere where an analog signal has to be processed, stored, or transported in digital form. The ADC covers a wide range of applications, including music recording, computer data storage, video/audio processing, mobile communication, measurement system, and so on. The ADC can be implemented, as well known to one of ordinary skill in the art, in many different types, such as a flash ADC, a successive-approximation (SAR) ADC, a sigma-delta ADC, or a pipeline ADC. Generally, applications with lower sampling rates are still the domain of the successive approximation register (SAR) and more recently, sigma-delta ADCs. The highest sampling rates are still obtained using flash ADCs. Nonetheless, pipeline ADCs of various forms have improved greatly in speed, resolution, dynamic performance.
The pipeline ADC uses two or more steps of subranging. First, a coarse conversion is done based on an input analog signal. In a second step, the difference to the input analog signal is determined with a digital to analog converter (DAC). This difference is then converted finer, and the results are combined in a last step. An example of pipeline ADC can refer to the document of Chun C. Lee and Michael P. Flynn, entitled “A 12 b 50 MS/s 3.5 mW SAR Assisted 2-Stage Pipeline ADC”, which is hereby incorporated by reference.
Please refer to FIG. 1, which illustrates the proposed pipeline ADC architecture of the abovementioned document. The Stage 1 of pipeline ADC 100 comprises a 6 bit SAR ADC 110 employed for a coarse conversion to generate a digital code DOUT1 of 6 bits according to input signal VIN and the adder 120 determines a difference between the input signal VIN and the signal V1 proportional to the digital code DOUT1. Accordingly, an amplifier 140 is employed for amplifying the difference to generate a residual signal VRES and a 7 bit SAR ADC 150 performs a fine conversion on the residual signal VRES to generate a digital code DOUT2 of 7 bits. Finally, a digital error correction block 160 combines and corrects the digital code DOUT1 and the digital code DOUT2 for obtaining a digital code DFINAL, which is the conversion result of the input signal VIN. The architecture proposed uses a SAR ADC instead of the conventional flash ADC architecture, as a first stage. This eliminates all the drawbacks of a first stage of the flash ADC architecture. In more detail, this eliminate the dedicated sample and hold amplifier (SHA) which provide a stable held signal for flash ADC and MDAC in the first stage. Moreover, SAR ADC requires less power consumption and die area than flash ADC.
However, in the abovementioned architecture, since the first stage of the pipeline ADC 100 needs to resolve a large amount of bits (6 bits), the performance of the amplifier 140 is strictly demanded. For example, the bandwidth and the slew rate of the amplifier 140 should be large enough to make the difference between the input signal VIN and the signal V1 well-amplified, in order to make the residual signal VRES have a proper and exact scale. Only by doing so, the 7 bit SAR ADC 150 can correctly resolve the remaining bits, namely digital code DOUT2. Hence, the amplifier 140 will affect the performance of the pipeline ADC 100.
In view of above, under the prior-art architecture, the performance of the amplifier 140 becomes a most significant bottleneck of the pipeline ADC 100. If the amplifier 140 is not well-designed, the pipeline ADC will get a poor performance.